Réponse transitoire du condensateur haute tension pour la gradation pulsée UV

Réponse transitoire du condensateur haute tension pour la gradation pulsée UV

Abstract

Pulsed dimming switches a UV source between two power levels at 1–10 kHz, and every edge is a load step the capacitor bank must carry before the control loop reacts. This article derives the charge demand, the droop, the recovery time constant and the damping ratio for a 400 V bus, then gives six design steps that keep dose uniform in dimming mode.

1. Introduction

Pulsed dimming switches the UV source between two power levels at 1–10 kHz. It controls dose without shutters, saves energy between printed sheets and avoids the thermal shock that shortens lamp life.

It is also the hardest duty for the capacitive elements. Every dimming edge is a load step: the current demand jumps from the dim level to the full level, and the bank supplies that transition before the control loop reacts.

A rail that sags at the edge changes the dose at the start of each sheet. A rail that rings after the edge modulates the lamp current and prints banding across the substrate.

This article covers the charge arithmetic, the recovery and damping criteria, four field pain points, and six design steps that hold dose uniformity in dimming mode.

2. Mécanisme de base

2.1 Charge demand at the load step

A dimming edge is a power step. The charge it removes from the bus while the edge lasts sets the droop:

ΔQ = ΔP × t_step / V_bus

where ΔQ is the charge delivered during the edge, ΔP the load power step, t_step the interval in which the bank carries the load alone, and V_bus the bus voltage.

A 5 kW step held for 50 µs at 400 V draws 625 µC. The converter loop reacts in hundreds of microseconds, so the bank carries the whole edge at 5 kHz.

2.2 Droop from the bank capacitance

The droop follows from that charge and the bank value:

ΔV = ΔQ / C_bank = ΔP × t_step / (C_bank × V_bus)

where ΔV is the bus droop and C_bank the total bank capacitance. A 100 µF bank droops 6.25 V, which is 1.6% of a 400 V rail. A 1560 µF bank droops 0.4 V, which is 0.1%.

Stored energy scales the same way:

E_link = 0.5 × C_bank × V_bus²

where E_link is the energy stored in the bank in joules. The 1560 µF bank holds 125 J at 400 V, so a 0.25 J edge costs it 0.2% of that store.

2.3 Recovery time against the dimming period

After the edge, the converter replenishes the charge with a time constant set by the loop:

τ_rec ≈ C_bank × R_load / (1 + loop gain)

where τ_rec is the recovery time constant, R_load the equivalent load resistance, and loop gain the compensator gain at crossover.

A 5 kW load at 400 V is 32 Ω. With 1560 µF and a loop gain of 20, τ_rec is 2.4 ms. At a 5 kHz dimming rate the period is 200 µs, so the loop never finishes recovering before the next edge.

2.4 Ringing and the damping criterion

Every edge excites the resonance between the bank capacitance and the loop inductance:

f_ring = 1 / (2π √(L_stray × C_bank))

where f_ring is the ring frequency, L_stray the loop inductance including the bank ESL and the bus wiring, and C_bank the bank capacitance.

A 10 µF bank with 100 nH of stray inductance rings at 159 kHz, inside the band where lamp current modulation appears as banding. The loop impedance is Z0 = √(L_stray / C_bank) = 0.1 Ω.

The decay is set by the damping ratio:

ζ = (R_damp / 2) × √(C_bank / L_stray)

where ζ is the damping ratio and R_damp the total series resistance in the loop, made up of bank ESR plus any added damper.

A 12.5 A edge into that 0.1 Ω loop demands a 1.25 V excursion. With 10 mΩ of bank ESR, ζ is 0.05 and the rail sits outside a ±0.4 V dose window until 21 µs. Raising R_damp to 140 mΩ lifts ζ to 0.7 and caps the excursion at 0.41 V, gone by 1.3 µs.

Fig. 1 — 159 kHz ringing keeps the 400 V rail outside its ±0.4 V dose window until 21 µs; 140 mΩ of damping caps that edge at 0.41 V, gone by 1.3 µs.

3. Points faibles en matière d'ingénierie

Pain Point 1: First-edge dose error

The first dimming pulse after a standby period sees a bank that is charged but cold. Its ESR and its capacitance both differ from the warm value, so the droop differs and the first sheet receives a different dose.

The defect shows up only at the start of each job, and the ink supplier gets the blame.

Pain Point 2: Ringing-induced banding

After every edge the bus rings at 100–500 kHz, and the lamp current follows the ring. The dose then modulates periodically across the substrate.

The banding is absent at nominal power and appears only in dimming mode, which makes it one of the hardest defects to reproduce on a test bench.

Pain Point 3: Thermal micro-cycling fatigue

Each dimming pulse heats and cools the dielectric. At 5 kHz that is 5,000 thermal micro-cycles per second, a fatigue regime no steady-state qualification test covers.

Porous Class II ceramics develop micro-cracks under that cycling, and the cracks raise tanδ, which raises self-heating and opens more cracks.

Pain Point 4: PD erosion under transient stress

The dimming edge superimposes a fast voltage swing on the DC rail. At the high-voltage filter and coupling sites the swing can excite partial discharge in an internal void even when the DC operating point is PD-free.

Erosion accumulates over millions of cycles, and the part fails short at the worst moment in the production schedule.

4. Étapes de conception

Strategy 1: Size the bank from the step equation

Compute C_bank from ΔV = ΔP × t_step / (C_bank × V_bus), using the worst-case dimming edge and a droop allowance of 0.1% of the rail.

For a 5 kW, 50 µs edge at 400 V that gives 1560 µF. A bank sized on average load instead lands near 100 µF and droops 6.25 V at every edge.

Strategy 2: Specify low-ESR Class I parts for the bank

Utilisez le diélectrique de classe I with tanδ below 0.1% so the bank impedance stays low and predictable, and the droop calculation holds at every temperature between −40 °C and +125 °C.

Class I capacitance also holds under DC bias, so the value used in the calculation is the value the hardware delivers.

Strategy 3: Tune the ringing with a damping element

Add series resistance until ζ exceeds 0.7. For a 10 µF bank with 100 nH of stray inductance that means 140 mΩ in total, so a 130 mΩ résistance à couche épaisse in series with the bank covers it.

Where the loss has to stay out of the bank itself, a condensateur à film in parallel provides the damping in its own ESR. Verify the decay on the oscilloscope with the real dimming waveform.

Strategy 4: Verify PD under the dimming waveform

Request pulse-PD data taken with the actual dimming edge, because a DC PD test does not reproduce the transient swing. Accept parts with PD below 5 pC under that waveform.

For the temperature reference in the same test, a résistance d'échantillonnage with a published coefficient keeps sensor drift out of the result.

Strategy 5: Life-test at the dimming rate

Run 10 million dimming edges at the worst-case rate and the worst-case ambient, measuring capacitance and tanδ at intervals.

Reject the design if tanδ rises above 0.1% or capacitance drifts more than 2%. That screen catches the micro-cycling failure long before the field does.

Strategy 6: Compensate the first edge in firmware

Predict the first-pulse droop from the measured bank temperature and apply a feed-forward term to the dimming command.

The job-start dose error then disappears without a hardware change, and the correction costs one table lookup.

Paramètre de composant	Valeur typique	Condition de test
Tension nominale (série HVCT8G)	10 kV DC	haute tension 1.5× pendant 60 s
Capacitance	4700 pF ±20% (472M)	1 MHz, 1 V efficace
ESR à 1 MHz	inférieur à 50 mΩ	à tanδ 0.1 % ou mieux
Inductance de boucle (accord E40)	en dessous de 8 nH	Espacement des bornes de 40 mm
La resistance d'isolement	supérieure à 10 GΩ à 500 V CC	25 °C, 60 % HR
Plage de température	−40 °C à +125 °C	Série IEC 60068-2
Capacité dv/dt d'impulsion	au-dessus de 50 kV/µs	à la tension nominale

5. HVC N4700 capacitors for pulsed dimming

Three requirements drive the choice at this node: droop that stays inside the dose allowance at every temperature, damping that does not come from a lossy dielectric, and PD margin under the dimming edge itself. HVC builds Class I parts for that set, from a 6,000 m² owned factory in Dongguan, across 1 kV to 100 kV.

Six paramètres importants ici

• N4700 Class I dielectric with ±30 ppm/°C holds the bank value used in the droop calculation across the whole cabinet temperature range, so the ΔV = ΔP × t_step / (C_bank × V_bus) figure is met on a cold morning and a hot afternoon.
• tanδ below 0.1% at 1 kHz keeps the bank ESR in the low milliohm range, so the damping that is added stays measurable.
• No DC-bias derating means the capacitance on the label is the capacitance at the 400 V rail, and at the 20 kV lamp stage.
• PD below 5 pC at 1.2× rated voltage is guaranteed per part, which covers the high-voltage coupling sites where the dimming swing is largest.
• A 1–100 kV range with disc and 441 screw-terminal packages serves the bus bank and the lamp stage from one qualified family. condensateurs poignée de porte carry the high-voltage sites.
• HVC's 40 kV / 441 screw-type capacitor replaced a first-tier international brand in field-service programmes where every power transition runs without disturbing a nanometer-scale process. The range matches the parameters of Vishay et les composants haute tension TDK.

Livraison et support

Standard parts ship in 4–8 weeks, and matched bank sets in 6–10 weeks. HVC applications engineering reviews the bank sizing, the damping network and the dose allowance against your dimming waveform.

Send the dimming waveform, the load-step profile, the bus voltage and the dose tolerance. HVC returns a bank-sizing calculation, a damping recommendation and a PD-screened sample for your own transient testing, with data sheets in hand within two weeks.

6. Questions fréquentes

Q1: How do I size the dimming bank?

From the step equation. Rearrange ΔV = ΔP × t_step / (C_bank × V_bus) for C_bank, insert the worst-case edge and the droop allowance. A 5 kW edge of 50 µs at 400 V with a 0.4 V allowance needs 1560 µF.

Q2: Why does 100 µF fail at this duty?

Because the droop scales as 1/C_bank. At 100 µF the same 625 µC edge produces 6.25 V, which is 1.6% of a 400 V rail and enough to change the delivered UV dose at the start of every sheet.

Q3: What damping ratio do I need?

ζ of 0.7 or higher. At ζ = 0.05 the rail stays outside a ±0.4 V dose window until 21 µs, about a tenth of the 200 µs period at 5 kHz. At ζ = 0.7 the same edge peaks at 0.41 V and is gone by 1.3 µs.

Q4: Where does the damping resistance come from?

From bank ESR plus an added element. A 10 µF bank with 100 nH of stray inductance needs 140 mΩ total for ζ = 0.7, so a 130 mΩ series resistor or a parallel film capacitor supplies the rest. The added loss stays under 1 W at 12.5 A rms.

Q5: Does the control loop recover the rail between edges?

No. With 1560 µF, a 32 Ω load and a loop gain of 20, the recovery time constant is 2.4 ms, which is 12 periods at a 5 kHz dimming rate. The bank supplies each edge and the loop trims the average.

Q6: How do I qualify a part for pulsed dimming?

Run 10 million dimming edges at the worst-case rate and temperature, measure capacitance and tanδ at intervals, and reject if tanδ passes 0.1% or capacitance drifts more than 2%. Add a pulse-PD test with the real edge, and accept only parts below 5 pC under that waveform.

7. Références

1. E. Kuffel, WS Zaengl, J. Kuffel, Principes fondamentaux de l'ingénierie haute tension, 2e éd., Newnes, 2000.
2. Mohan, N., Undeland, TM et Robbins, WP, Électronique de puissance : convertisseurs, applications et conception, 3e éd. Hoboken, NJ : John Wiley & Sons, 2003.
3. Avis MIL-HDBK-217F 2, Prédiction de la fiabilité des équipements électroniques 1995.
4. CEI 60384-1:2021, Condensateurs fixes pour équipements électroniques - Partie 1 : Spécifications générales, 6e éd. Genève : CEI, 2021.
5. CEI 61071:2017, Condensateurs pour l'électronique de puissance, Éd. 2.0. Genève : Commission électrotechnique internationale, 2017.
6. GB/T 17702-2021, 电力电子电容器 (Condensateurs pour l'électronique de puissance). Pékin : 国家市场监督管理总局, 2021.
7. H. Wang et F. Blaabjerg, Fiabilité des condensateurs pour les applications de liaison CC dans les convertisseurs d'électronique de puissance — Un aperçu, IEEE Transactions on Industry Applications, vol. 50, no. 5, pp. 3569-3578, 2014. https://doi.org/10.1109/tia.2014.2308357.
8. L. Zheng, L. Zhu, J. Liu, Z. Di et S. Ji, Caractéristiques d'auto-réparation d'un condensateur à film métallisé sous tension superposée continue et alternative avec harmoniques, dans la conférence IEEE 2022 sur l'isolation électrique et les phénomènes diélectriques (CEIDP), pp. 175-178, 2022. https://doi.org/10.1109/ceidp55452.2022.9985286.
9. AND9800/D — Sélection du condensateur d'amortissement pour les applications d'entraînement de moteur (Tableau 15 Données de test), onsemi, AND9800-D, https://m.onsemi.jp/pub/Collateral/AND9800-D.PDF .
10. Condensateurs à impulsions à film métallisé MKP — Présentation du produit, KEMET Electronics, https://www.digikey.com/en/product-highlight/k/kemet/mkp-metallized-film-pulse-capacitors .
11. Équipe d'ingénierie des applications HVC, Condensateur céramique haute tension Ressources techniques, https://www.hv-caps.com